1. Technical Field
Various embodiments relate generally to a semiconductor apparatus, and more particularly to a clock duty cycle correction method of a semiconductor apparatus.
2. Related Art
A duty cycle of a clock represents a ratio of a pulse width with respect to a pulse cycle of the clock. In other words, the duty cycle is the ratio of the duration of an active state to the total period of a clock signal. In general, a digital clock having a duty cycle of 50:50 is used in a semiconductor integrated circuit, which indicates that the width of a high level period of the clock is substantially equal to the width of a low level period of the clock.
In some digital electronic devices, it is important to precisely control the duty cycle of the clock to be 50:50. For example, in a synchronous semiconductor apparatus in which data is input/output in synchronization with a clock, when the duty cycle of the clock is not precisely controlled, data may be distorted.
Recently, in order to improve an operation speed, a DDR (Double Data Rate) synchronous semiconductor apparatus is being used. Since data is input/output at a falling edge of a clock as well as a rising edge of the clock, there is a need to sufficiently ensure a data margin by controlling the duty cycle of the clock.